ISL97635IRZ【PDF 20/28 页】IC LED DRVR WHT/RGB BCKLGT 24QFN

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ISL97635

TABLE 3. OPERATING MODES SELECTED BY DEVICE

CONTROL REGISTER BITS 1 AND 2

PWMI = is the percent duty cycle of the PWMI

For example, the Cbt = 50% duty cycle programmed in the

PWM_MD PWM_SEL

MODE

SMBus Register 0x00 and the PWM frequency is tuned to be

X

1

0

1

0

0

PWMI Mode

SMBus Mode

SMBus and PWMI Mode with DPST

200Hz with an appropriate capacitor at the FPWM pin. On the

other hand, PWMI is fed with a 1kHz 30% high PWM signal.

When PWM_SEL = 0 and PWM_MD = 0, the device is in DPST

operation where DPST brightness = 15% PWM dimming at

The PWM_SEL bit determines whether the SMBus or PWMI

input should drive the output brightness in terms of PWM

dimming. When PWM_SEL bit is 1, the PWMI drives the

output brightness regardless of what the PWM_MD is.

When the PWM_SEL bit is 0, the PWM_MD bit selects the

manner in which the PWM dimming is to be interpreted;

when this bit is 1, the PWM dimming is based on the SMBus

brightness setting. When this bit is 0, the PWM dimming

reflects a percentage change in the current brightness

programmed in the SMBus Register 0x00, i.e. DPST

(Display Power Saving Technology) mode, as shown in

Equation 15:

200Hz.

? All reserved bits return a “0” when read.

? All reserved bits have no functional effect when written.

? All defined control bits return their current, latched value

when read.

? A value of 1 written to BL_CTL turns on the BL in 4ms or less

after the write cycle completes. The BL is deemed to be on

when Bit 3 BL_STAT of Register 0x02 is 1 and Register

0x09 is not 0. See Figures 23 and 24.

? A value of 0 written to BL_CTL immediately turns off the BL.

The BL is deemed to be off when Bit 3 BL_STAT of Register

0x02 is 0 and Register 0x09 is 0. See Figures 23 and 24.

DPST Brightness = Cbt × PWMI

(EQ. 15)

? **Note that the behavior of Register 0x00 (Brightness

Where:

Cbt = Current brightness setting from SMBus Register 0x00

without influence from the PWMI

Control Register) is affected by certain combinations of the

control bits, as shown in Table 3 “Operating Modes

Selected by Device Control Register Bits 1 and 2.”

REGISTER 0x00

PWM BRIGHTNESS CONTROL REGISTER

BRT7

Bit 7 (R/W)

BRT6

Bit 6 (R/W)

BRT5

Bit 5 (R/W)

BRT4

Bit 4 (R/W)

BRT3

Bit 3 (R/W)

BRT2

Bit 2 (R/W)

BRT1

Bit 1 (R/W)

BRT0

Bit 0 (R/W)

BIT ASSIGNMENT

BRT[7..0]

REGISTER 0x01

BIT FIELD DEFINITIONS

= 256 steps of PWM brightness levels

FIGURE 23. DESCRIPTIONS OF BRIGHTNESS CONTROL REGISTER

DEVICE CONTROL REGISTER

RESERVED RESERVED RESERVED RESERVED RESERVED

PWM_MD

PWM_SEL

BL_CTL

Bit 7 (R/W)

Bit 6 (R/W)

Bit 5 (R/W)

Bit 4 (R/W)

Bit 3 (R/W)

Bit 2 (R/W)

Bit 1 (R/W)

Bit 0 (R/W)

BIT ASSIGNMENT

PWM_MD

PWM_SEL

BL_CTL

BIT FIELD DEFINITIONS

= PWM mode select bit (1 = absolute brightness,

0 = % change) default = 0

= Brightness control select bit (1 = control by

PWMI, 0 = control by SMBus) default = 0

= BL On/Off (1 = On, 0 = Off) default = 0

FIGURE 24. DESCRIPTIONS OF DEVICE CONTROL REGISTER

20

FN6434.2

December 22, 2008

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